Stepped sinusoidal-like waveform generating inverter circuit

ABSTRACT

An inverter circuit for generating a stepped sinusoidal-like output has a transformer with a center tapped primary winding, a source of D.C. voltage connected between the center tap point and ground or other reference point, and a pair of switch means respectively connected between the opposite ends of the primary winding and the common reference point, which switch means are rendered conductive sequentially and during spaced intervals during which an output is desired. Primary winding shunting switch means is connectable across all or half of the primary winding to short circuit that part of the winding carrying current to produce a substantially zero output between each pair of said spaced intervals. The primary winding shunting switch means most advantageously is a transistor or the like whose load terminals are connected between the center tap point of the primary winding and the juncture of a pair of diodes respectively connected to the opposite ends of the primary winding.

United States Patent 1 Bates STEPPED SINUSOIDAL-LIKE WAVEFORM GENERATING INVERTER CIRCUIT [75] Inventor: James W. Bates, Palos Verdes 211 App]. No.: 204,237

[52] 0.8. CI. 321/27 MS, 321/45 R [51] Int. Cl. H02m 7/52 [58] Field of Search 321/9 A, 11, 27 R, 321/18, 27 MS, 45R, 45 C, 45 SW [56] References Cited UNITED STATES PATENTS 3,031,629 4/1962 Kadri 321/27 MS 3,205,424 9/1965 Bates 321/18 3,328,664 6/1967 Baude 321/27 MS 3,408,553 10/1968 Bishop 321/45 R X 3,416,062 12/1968 Bernhard et a1. 321/27 MS 3,432,737 3/1969 Hunter et a1 321/45 R X Primary Examiner-William M. Shoop, Jr.. Attorney-Wallenstein, Spangenberg, Hattis &

Strampel Oct. 23, 1973 [57] ABSTRACT An inverter circuit for generating a stepped sinusoidallike output has a transformer with a center tapped primary winding, a source of DC. voltage connected between the center tap point and ground or other reference point, and a pair of switch means respectively connected between the opposite ends of the primary winding and the common reference point, which switch means are rendered conductive sequentially and during spaced intervals during which an output is desired. Primary winding shunting switch means is connectable across all or half of the primary winding to short circuit that part of the winding carrying current to produce a substantially zero output between each pair of said spaced intervals. The primary winding shunting switch means most advantageously is a transistor or the like whose load terminals are connected between the center tap point of the primary winding and the juncture of a pair of diodes respectively connected to the opposite ends of the primary winding.

11 Claims, 9 Drawing Figures United States Patent [1 1 1 3,768,000 Bates Oct. 23, 1973 Ea I 242 MAJOR CIRC UIT J TURN ON DRIVE MEANS MINOR CIRCUIT TURN 'ON DRIVE MEANS NA JOR CIRCUI T TURN-OFF DRIVE MEANS MINOR C/RCUI T TURN-0F F D)?! VE MEA NS I Eq. v

MAJOR CIRCUIT TURN-0N omvs MEANS MINOR CIRCUIT TURN -ON DR IVE MEANS 32 TURN OFF I AID/N6 MEANS '1- MA JOR CIRCUIT 32a. TURN-OFF DRIVE 5: nan/vs i J I MINOR CIRCUIT TURN-OFF v DRIVE MEANS ZNvEN TOR STEPPED SINUSOIDAL-LIKE WAVEFORM GENERATING INVERTER CIRCUIT This invention relates to apparatus for generating relatively low frequency sinusoidal-like signals from a source of direct current, using relatively compact, light-in-weight components, and has its most important application in direct current powered single phase sinewave power supplies capable of delivering substantial amounts of power for various applications, such as power supplies for satellites and aircraft, where size, weight and/or cost limitations are important considersti m- The generation of low frequency sinewave current of substantial magnitude generally requires extremely bulky equipment, whether it be an electromechanical device, such as motor generator equipment, or electronic circuits. Electronic circuits commonly generate sinewave currentfrom the output of a direct current energized square wave generator or inverter circuit whose output appearing across the output of a transformer is filtered to provide a substantially sinusoidal waveform. A relatively recent development in electronic sinewave generator circuits produce an approximation of a'sinewave signal by the superpositioning of a number of square topped pulses of varying width and polarity to provide a stepped waveform whose general outline resembles a sinewave.

US. Pat. No. 3,579,081 discloses, as examples of a basic invention also utilized in the present invention, several low frequency sinusoidal sinewave generator circuits each comprising a major and one or more minor bridge circuits each comprising two circuit branches including a pair of current control devices or switches like transistors connected in series circuit relation across a source of DC. voltage. Each pair of switches in each circuit branch are rendered alternately conductive so only one of these devices is conducting at a time. Different complementary alternating voltage outputs, which suddenly vary between various finite values and zero at different instants of time, are obtained across the output terminals of each of the bridge circuits located at the junctures between the pairs of switches in the circuit branches. The voltage outputs have a finitevalue about equal to the output of the DC. voltage source as two non-corresponding pairs of switches of the circuit branches are rendered alternately conductive. In such bridge circuits, the maximum voltage which is applied to each of the switches is the applied DC. voltage, and load current flows through two switches connected in series across the applied D.C. voltage. These complementary voltage outputs are added together to produce a stepped sinusoidal-like voltage waveform.

i The present invention provides stepped sinusoidallike waveforms preferably-utilizing at least a pair of center-tapped transformer inverter circuits which provide different component square topped voltage waveforms which suddenly vary between various finite values and zero at different instants of time and each of which circuits requires three rather than four switches and has load current flowing only through one of the switches at a given time. This has the advantage of eliminating the voltage drop across one switch to increase the efficiencybf the circuit as well as reducing the cost and increasing the reliability thereof. However, the use of a cententa'pped transformer inverter circuit produces voltage conditions where the main inverter switches must withstand twice the applied DC. voltage, and so this circuit has its most advantageous application in lower voltage application than the bridge referred too. In a center-tapped transformer inverter circuit, a pair of main transistor switches or the like are connected across the opposite ends of a center-tapped primary winding of a transformer and a common reference point. A source of DC voltage is connected between the center tap of the primary winding and the common reference point. Alternately rendering the transistors conductive over spaced intervals results in the flow of current in opposite directions respectively through the halves of the primary winding to produce voltage pulses of opposite polarity across the secondary winding of the transformer. To obtain a sudden zero output between the desired spaced conducting intervals of the transistors without any build up of undesirably high voltages across the transformer primary winding, a short circuit is directly provided across a winding of the transformer most advantageously across the half of the primary winding conducting current at a given instant of time. In the latter case, a transistor switch or the like is connected between the center tap of the primary winding and the juncture of a pair of diodes respectively connected to the opposite ends of the primary winding so as to complete paths of current flow in the associated halves, of the primary winding. Each diode and the load terminals of the latter transistor effectively short circuits the associated half of the primary winding which thereby reflects a short circuit of zero impedance condition across the terminals of the secondary winding. Properly timed control signals are fed to the control electrodes of the various transistors or other switch devices referred to to produce the desired plus, minus or zero output conditions across the transformer secondary winding.

In high power capacity inverter circuits, it is usually desirable to use transformer coupled drive amplifiers. Any feature which reduces the number of transformers in the drive amplifiers will desirably materially reduce the cost, weight and size of an inverter system. With this end in mind, another feature of the invention is the utilization of a common drive transformer for two or more of the inverter switches of the same inverter circuit and/or for the two inverter circuits of the stepped sinusoidal like waveform generator circuit, even when the switches controlled by the common drive transformer have different conduction patterns. A still further feature of the invention provides more perfect zero output intervals which, in the absence of such feature, is not achieved because of a transformer coupled voltage drop appearing across the primary winding shunting transistor switch and diodes.

The above and other advantages and features of the invention will become apparent upon making reference to the specification to follow, the claims and the drawings wherein:

FIG. 1 is a simplified diagram of a center-tapped transformer inverter circuit designed in accordance with the present invention;

FIG. 2 shows the output from tthe inverter circuit of FIG. 1; 7

FIG. 3 shows two center-tapped transformer inverter circuits each providing complementary pulsed output waveforms andconnected together to provide a more nearly sinusoidal-like resultant output;

FIG. 4 is an exemplary circuit diagram for the circuit shown in FIG. 3;

FIG. shows various voltages present at various designated points in FIG. 4;

FIG. 6 shows an improvement in' the center-tapped transformer inverter circuit shown in FIG. 4 which pro- Refer now to FIG. 1 which shows the simplest form of the invention. This inverter circuit, generally indicated by reference numeral 2, includes a transformer 4 having a center-tapped primary winding formed by two primary-halves 4a and 4b, and a secondary winding 4c across which an output like El shown in FIG. 2 appears-[Switches S1 and S2, which may be transistors,

are connected respectively between the ends of the primary winding halves 4a and 4b and a common reference point or ground 5. A source of D.C. voltage 6, which may be abattery, is connected between the center-tapped point of the said primary winding and ground. Switch means S3, which may include a control switch like a transistor and diodes to be described, is connected across the primary winding 4a. When the control switch involved is rendered conductive, a short circuit-forming path is formed no matter what the polarities of the voltages or currents in the circuit are at the time involved. This short circuit is then reflected across the secondary winding 40 to provide an effective near zero impedance across the secondary winding to effect a zero voltage output condition for the inverter circuit. A control circuit 7 is provided having a number form, one or more other pulse waveforms can be added to the waveform E1 shown in FIG. 2 as, for example, the waveform E2 shown in FIG. 5, which for each half cycle of waveform E1 supplies additive pulses during the first and last 30 interval and during the middle interval of each half cycle. These pulses have an amplitude approximately one-third that of the amplitude of the waveform E1. (Other more complex waveforms may be added, such as those shown in said U.S. Pat. No. 3,579,08l). Waveform E0 in FIG; 5 represents the summation of the waveforms E1 and B2. In the present invention, to provide a waveform like E2, a second center-tapped transformer inverter circuit 2 is provided in addition to the inverter circuit 2, as shown in FIG. 3. (The inverter circuits 2 and 2 will sometimes be referred to as the major and minor inverter circuits). The inverter circuit 2 shown in FIG. 3 is substantially identical to the inverter circuit 2 (and corresponding parts thereof have been similarly identified in FIG. 3 except for the addition of a prime to the reference characters) except that the turnsratio of the primary and secoridary windings of the transformers 4 and 4"and the control signal waveforms produced by control circuits 7 and 7 are different. The secondary windings4c and 4c are connected in series acrossoutput'terminals8 a'nd"10 at which the output. waveform E0 inFIG. 5 appears. .0 i

Refer now to the circuit diagram shown in FIG. 4, which shows a transistorized embodiment of the invention where certainportions .ofthe control, circuitry 7 and7' used to control the-primary windingshort circuiting switch means 83 and S3 are combined intoa common control circuit. As thereshown, the various transistor switches S1, S2, 51- and S2 are NPN type transistors with the collectors 12c of the transistor switches 81 and S2 and the collectors 12c of the transistor switches S1 and S2 respectively connected to the outer ends of the associated primary winding halves 4a-4b and 4a'-4b'. To provide a path for current flow for out-of-phase current components where reactive of different output lines carrying various control signals and respectively connected to switches S1 and S2 and the control switch-of switch means S3 to control the conduction and non-conduction thereof. vWhen the switch S1 is rendered conductive for a given interval,

- current flows through primary winding half 4a and the switch S1 connected in series across the terminalsof the D.C. voltage source 6, to induce aflat topped pulse of one polarity across the secondary winding 4c of the transformer 4. Such a pulse lasting for a 120 half cycle centered interval is shown during the first half cycle of the waveform E1 shown" in FIG. 2'. When the switch S2 2. To quickly terminate the flow of current in the primary winding to effect a zero output condition interval (like the 60 zero output interval between the positive and negative pulses of the waveform Elshown in FIG. 2), the control switch portion of switch means S3 is rendered conductive for the interval involved.

the negative going portion of the waveform E1 in FIG. 1

points of pairs of diodes 16-18 and 16 18". The .ar sssit s pairs 6: nd r respectively connected to the collectors 14c-l4c of the transistors 14-14, and the cathodes thereof are respectively connected to the outer ends of the primary windings of the associated transformers 4 and 4. When current is flowing through the primary winding half 4a or 4a, the conduction of the transistors 14 or 14' will establish a current path for the current flowing in the associated winding half 4a or 4a, and to effectively short circuit the associated transformer secondary winding 40 and prevent the build-up of high voltages when the associated transistor switch S1 or S2 is rendered non-conductive. This current path includes the emitter and collector of the transistor 14 or 14' and the'diode 16 or 16. Similarly, when current is flowing in the primary winding half 4b or 4b, the conduction of transistor 14 or 14' establishes a short cu forming P t a r s tb as i sd p mary winding half 4b or 4b and including the emitter and collector of the transistor 14 or 14 and the associated diode 18 or 18. In FIG. 4, a common source of D.C. voltage 6 is utilized for both major and minor inverter circuits 2 and 2. Accordingly, the

positive terminal of the D.C. voltage source 6 is' connected to the center-tap points of the primary windings of the transformers 4 and 4' and the negative terminal thereof is grounded.

The bases 12b of the transistor switches S1 and S2 of the major inverter circuit 2 are respectively connected to outputs 24a and 24b of a major circuit turn-on drive means 24 at which outputs the control signal waveforms 3a and 3b shown in FIG. 5 appear. Each of these waveforms provides a positive output during the intervals at which the associated transistors are to be rendered conductive which, in the example of the invention being described, is a centered 120 interval for one half cycle of each cycle of operation of the inverter circuit. Similarly, the bases 12b of the transistor switches S1 and S2 of the minor inverter circuit 2' are respectively connected to control signal outputs 24a and 24b at which the control signals Ea and Eb'shown in FIG. 5 appear. Each of the waveforms Ba and Eb provide a 30 positive pulse for the first and last 30 intervals and a centered 60 positive pulse of the half cycle during which the associated transistor switch is to be rendered conductive. Such pulses will render the associated NPN transistors conductive duringthe period such positive pulses exist.-

For high power inverters, a simple drive circuit for the primary wining bypassing transistor switches 14 and 14 would probably not suffice. Accordingly, the circuit of FIG. 4, which is assumed to be one requiring a relatively high power drive to the transistors 14-14 includes a unique control circuit which utilizes only one main drive transformer for both the major and minor inverter circuits. To avoid transformer core saturation, it is important that, cover a cycle of operation of the transformer involved, approximately the same amount of positive and negative ampere turns of flux generating power are produced within the transformer core. It should be observed that the zero outputintervals of the output waveforms E1 and E2 of the major and minor inverter circuits, during which the primary winding bypassing transistors 14-14' are to be respectively conductive, occur at different intervals of time, and over a cycle of operation of the inverter circuit occupy the same total periods, namely 240 (120 each half cycle). This fact is taken advantage ofin the design of the drive circuit.

Accordingly, the turn-off drive circuit includes a drive transformer 26 with a center-tapped primary winding having primary windings halves 26a 26b, the juncture of which is connected to one of the terminals of a source of D.C. voltage, a positive terminal in the exemplary circuit being described, which may be the positive terminal of the D.C. voltage source 6. Transformer 26 has a center-tapped secondary winding with secondary winding halves 26c 26d. The center-tap point of the secondary winding is connected to the positive terminal of the D.C. voltage source 6 to which the emitter l4e-l4e of the transistors 14-14 are also connected. The outer ends of the secondary winding halves 26c 26d are respectively connected by conductors 27-27 to the basesll4b-l4b' of the PNP transistors 14-14 which require a negative voltage to render them conductive. The voltage appearing between the outer terminal of the secondary wind half 26c and the positive center tap point thereof control the conduction of the transistor 14, and the voltage appearing between the outer terminal of the secondary winding half 26d and the positive center tap point thereof controls the conduction of the transistor 14'.

The outer terminals of the primary winding halves 26a 26b are respectively connected to the collectors 18c-30c of a pair of NPN transistors 28 30 forming part of an inverter circuit. The emitters 28e-30e of the transistors 28-30 are shown connected to a common ground point, and the bases 28b 30b thereof respectively are shown connected to the output terminals 32a-34a of major and minor circuit turn-off drive means which generate the control signal waveforms Ec-Ec' shown in FIG. 5, which respectively render NPN transistor switches 28-30 conductive during the positive 1 amplitude intervals of the waveforms Ec-Ec'. It will be noted that the control signals Ec Ec' fed to the bases 28b-30b have their positive l amplitude levels at different instants of time and, over a full cycle, the sum of the l amplitude intervals thereof, is the same for the-two waveforms. Since conduction of transistor switches 28-30 effects current flow respectively in opposite directions through primary winding halves 26a-26b, the plus and minus ampere turns generated in the transformer 26 over an operating cycle are equal, providing a balanced operation of the transformer.

When transistor 28 is conductive and current flows through the upper primary winding half 2611 of the transformer 26, the outer or upper terminal of the secondary winding half 26c viewed in FIG. 4 will be negative with respect to the positive center tap point thereof and the outer or bottom terminal of the secondary winding half 2611 will be positive with respect to the positive center tap point thereof. Since these terminals are respectively connected by the conductors 27-27 to the bases of PNP transistors 14-14 where a negative voltage effects conduction and a zero or positive voltage effectnon-conduction thereof, it is apparent that the intervals during which transistor switch 28 is conductive will only have an effect upon the transistor 14 of the major inverter circuit 2. Similarly, when the transistor 30 is rendered conductive and current flows through the bottom primary winding half, the bottom or outer terminal of the secondary winding half 26b will be negative with respect to the positive center tap point thereof and the outer or upper terminal of the secondary winding half 260 will be positive with respect to the center tap point thereof. Conduction of the transistor 30 will, therefore, only result in the conduction of the transistor 14 of the minor inverter circuit 2'.

In order to effectively terminate all current flow in the transformer 26 during those intervals when the transistor switches 28-30 are both to be in a nonconductive state, an additional secondary winding, which is illustrated as center-tapped winding having secondary winding halves 26e-26f, is provided on the transformer 26, so that one or the other of these winding halves can be short circuited. This has the same effect as short circuiting the .primary winding. The juncture points of the secondary winding halves 26e-26f is grounded, and the outer terminals thereof are respecswitch'36, the same becomes conductive to effectively short circuit that secondary winding half 26e or 26f across which a voltage is induced of a polarity which effects conduction of the associated diode 38 or 40.

Refer now to FIG. 6 which show a further improvement in the inverter circuits 2 2' shown in FIG. 4. When current flows through either of the primary winding bypassing transistors 14 or 14' and the ssociated diodes 16-18 or 16'-18, the voltage drop occurring across these elements acts as a low voltage source of, for example, the order of magnitide of l k volts. This voltage source is stepped up by the inductive coupling between the associated primary winding half 4a-4a' or 4b-4b, and appears as an undesired voltage, for example, three or four times this amount across the associatedfsecon dary winding 40 or 40. In the preferred form of the invention,fthis voltage is substantially eliminated by circuitry like that shown in FIG. 6

which includes the addition of a low power transformre 44 having a primary winding 44a and secondary winding 44b 44b. One of the corresponding terminals of primary winding 44a is shown grounded and the other terminal thereof isconnecte i to the output 48a of a circuit turnoff drive means 48 which is a circuit which generates, for example", the waveform Ee shown in FIG.

6A whenthe inverter circuit involved is the major inverter'circuit 2, and the waveform Ee' shown therein when the inverter circuit involved is the minor inverter circuit 2. As shown in FIGS. 6A, the waveforms Be and Be comprises pulses alternating between apositive l and a negative I amplitude level during intervals which the primary circuit shorting transistors 14-14' areconductive. One of the corresponding ends of the secondary windings 44b-44b (the upper ends as illustrated)'of the transformer 44 are respectively connected to the cathode of the diode 16 or 16' and the outer or bottom end of the primary winding half 4b or 4b ofthe transformer 4 or 4'. The bottom ends of the secondary windings 44b-44b are respectively connected to the outer or upper endof the primary winding half 4a or 40' of the transformer 4 or 4' and the cathode-of diode 18 or 18'. The anodes of the diodes 16- 18 or l6-'18' are respectively connected to the collector l4c-14c' of the transistor 14 or 14'. The cathodes of the latter diodes, instead of being connected to the outer ends of the primary winding halves 4a-4b or 4a'-4b' of the transformers 4 or 4' as in the case of the circuit of FIG. 4, are instead connected to the noncorresponding ends of the secondary windings 44b 44b. Accordingly, when the voltage at the end of the secondary winding 44b connected to the cathode of the associated diode 16 or 16' is negative with respect to the opposite end thereof, the end of the secondary winding 44b connected to the cathode of diode 18 or 18' will be positive with respect to the opposite end thereof, and visa versa. Thus, each half cycle, the polarity of the voltages induced into the secondary windings 44b-44b alternate from that present during the previous half cycle.

The phase of the voltage waveforms Be and He applied to the primary winding 44a-44b' of the transformerv 44 is such that the polarity of the voltages induced across the secondary windings 44b-44b cancel the voltage drop occurring across the conducting transistor 14 or 14' and the .then conducting diode 16 or 16', or 18 or 18'. The amplitude of the voltages induced in the secondary windings 44b-44b is such as substantially to'cancel out the voltage drops developed across the transistor 14 or 14' and the diodes 16-18 or 16"l8',so that there will be little or no resultant voltage coupled into the secondary windings 4c or 4c. (The polarities shown in FIG. 6 of the voltages involved correspond to the polarities of the voltages present during the conducting intervals of the diodes and transistor switches involved, which occur during different half cycles).

For especially high power inverter systems, such as for inverters above a kilovolt ampere of capacity, it is desirable also to utilize drive circuits for the main transistor switches 81-82 and S1-S2' of the major and minor inverter circuits 2 and 2 like that shown in FIG. 7. Such drive circuits are similar to the drivecircuits shown in FIG. 4 for-driving the primary circuit bypassing transistors 14-14. Accordingly, a transformer is provided having a center-tapped primary winding constituted by primary winding halves 50a-50b to the juncture point of which'is connected the positive terminal of a source of D.C. voltage, like the D.C. voltage source 6, and a center-tapped secondary winding having secondary winding halves 50c-50d, the juncture point of which is grounded. The opposite ends of the secondary winding halves 50c-50d are respectively connected to the bases of the associated pairs of main transistor switches 81-82 or Sl'-S2'. A pair of NPN transistor switches 52-54 are provided having collectors 52c-54c connected to the opposite ends of the primary winding halves 50a-50b, and grounded emitters. The bases 52b-54b of the transistor switches 52-54 respectively are connected to the output terminals 56a-56b of turnon drive means 56, which terminals respectively have the control voltage waveforms Ea-Eb' or Ea'-Eb shown in FIG. 5 applied thereto to effect the desired conduction of the transistor switches 52-54. To terminate conduction in the transformer windings during the intervals the transistor switches 52-54 are not to be conducting, a secondary windingcomprising secondary winding halves 50e-50f is provided onthe transformer 50, the juncture point of which is grounded and whose opposite ends are respectively connected through diodes 60-62 to the collector 58c of a NPN transistor 58 whose emitteris grounded and whose base is connected to the output terminal 64a of a turn-off drive means 64 which produces-a control voltage waveform having a positive l amplitude level, during those intervals when the transistors 52-54 are both non-conductive, namely during the l amplitude intervals of the waveforms Ec or E0 shown in FIG. 5.

It should be understood that filter circuits (not shown) would be connected to the output of the various generator circuits above described to provide a substantially ripple-free sinusoidal-like waveform.

The various specific forms of the present invention above described provide very effective, efficient, single phase stepped sinusoidal-like waveform generator circuits of minimum complexity, weight and size for appreciable' power handling capacities. Three such single phase circuit properly phased could provide a three phase system, where desired.

it should be understood that numerous modifications may be made in the most preferred forms of the invention described without deviating from the broader aspects thereof. For example, while an important specific aspect of the invention is the location of the short circuit producing switch means 3 as described across the primary windings of the transformer where in the battery operated systems, voltages of lower magnitude are present thereby requiring lower voltages and less expensive transistors, in accordance with the broader aspects of the invention, the switch means for effecting an effective short circuit across the secondary winding 4c of the output transformer 4 may be located across the secondary winding 40 as illustrated in FIG. 8. As there shown, a PNP transistor 14" is shown with its emitter 14a connected to the juncture of the cathodes of diodes l6a-18a whose anodes are respectively connected across the upper and lower ends of the secondary winding 4c, and its collector Me is connected to the juncture of the anodes of diodes l8b-l6b whose anodes are respectivelyconnected across the upper and lower ends of the secondary winding 40. The base 14b" of the transistor 14" is connected to the output of the control circuit 7 which provides pulses during those intervals when it is desired to produce a zero output for the inverter circuit. It is thus apparent that when the upper end of the secondary winding 4c is positive with respect to the bottom end thereof, a short circuit path is established extending through the diode 16a, the emitter and collector of transistor 14 and the diode 16. When the upper end of the secondary winding 40 is negative with respect to the bottom end thereof, a short circuit path is established extending through diode 18a,

the emitter to collector of transistor 14" and the diode 1 claim:

1. A stepped alternating voltage generating circuit comprising: a transformer having a center tapped primary winding and at least one secondary winding: a source of DC. voltage having a pair of DC. output terminals, said DC. output terminals being connected between a center tap point on said primary winding and a reference point; first and second switch means respectively connected between the ends of said primary winding and said reference point; control means for alternately rendering said switch means conductive during spaced intervals to effect current flow sequentially in opposite directions through different halves of said primary winding to generate pulses alternating in polarity in said secondary winding spaced by intervals where the output is substantially zero; and means for ensuring the sudden and continued disappearance in the output across said secondary winding during said spaced intervals including third switch means connectable across a winding of said transformer, and control means for rendering the latter switch means conductive during said spaced intervals wherein said third switch means is a current control device having a pair of load terminals connected in series with the center top point of said primary winding, and there is associated with said third switch means a pair of rectifier means connected respectively in the same sense between the load terminal of said current control device remote from said'primary winding and the opposite ends of said primary winding, to form respective paths shunting the respective halves of the primary winding to bypass the current flow therethrough.

2. A stepped alternating voltage generating circuit comprising: a major and a minor inverter circuit, each inverter circuit comprising a transformer having a primary winding and at least one secondary winding, a pair of DC. voltage input terminals connected between a center tap point on said primary winding and a reference point, first and second switch means respectively connected between the ends of said primary winding and said reference point, first control means for alternately rendering said first and second switch means conductive during spaced intervals to effect current flow sequentially in opposite directions through different halves of said primary winding to generate pulses alternating in polarity in said secondary winding spaced by intervals where the output is substantially zero, and

means for ensuring the sudden and continued disappearance in the output across said secondary winding during said spaced intervals comprising third switch means connectable across a winding of said transformer and second control means for rendering the latter switch means conductive during said spaced intervals; the control means ofsaid major and minor bridge circuits rendering the associated first, second and third switch means conductive in different but complementary conduction patterns so the summation of the outputs of the secondary windings of the associated transformers produces a stepped, sinusoidal-like waveform; and means connecting the secondary windings of the transformers of said major and minor bridge circuits in series voltage additive relation.

3. The circuit of claim 2 wherein said third switch means of each inverter circuit is a current control device having a pair of load terminals connected in series with the center tap point of said primary winding and a control terminal which effects conduction of the switch means when a drive signal of a given polarity is fed thereto by said second control means, and there is associated with each third switch means a pair of rectifier devices respectively coupled in the same sense between the load terminal of said current control device remote from said primary winding and the opposite ends of said primary winding, to form respective paths shunting the respective halves of the primary winding to bypass the current flowing therethrough.

4. The circuit of claim 2 where the conduction pattern of the first, second and third switch means of said major inverter circuit is that said first and second switch means are identically alternately rendered conductive during successive half cycles, each such switch means having one conducting interval occupying a majority of and centered in the half cycle involved, leaving relatively narrow non-conducting intervals at the beginning and end of the half cycle, and the third switch means is conductive during the intervals when said first and second switch means are not conductive; the conduction pattern of the first, second and third switch means of said minor inverter circuit is that said first and second switch means are identically alternately rendered conductive during successive half cycles, each such switch means having during each half cycle when the same is conductive a half cycle centered conducting interval and conducting intervals corresponding to the beginning and end of the half cycle, and the third switch means is conductive during the intervals when said first and second switch means are not conductive; the conduction pattern of the first, second and third switch means of said minor inverter circuit is that said first and second switch means are identically alternately rendered conductive during successive half cycles, each such switch'means having during each half cycle when the same is conductive only a half cycle centered conducting interval and conducting intervals corresponding to said narrow non-conducting intervals of the corresponding switch means of the major invertercircuihthe sum of the non-conducting intervals of the first and second switch means of the major inverter circuit over each cycle thereof being substantially the same as the sum of the non-conducting intervals of the first and second switch means of the minor inverter circuit; and said second control means of the said major and minor inverter circuits being a common inverter drivecircuit comprising a transformer having a center-tapped primary winding and at least one, secondary winding, a source of-D.C. voltage having a pair of D.C. output terminals, said D.C. output terminals being connected between a center tap point on said primary windingand a reference point, first and second switch means respectively'connected between the ends of said primarywinding and said reference point, the latter secondary winding having a center tap point coupled to said reference point pf saidmajor and minor inverter circuits and the opposite ends thereof being respectively connected to said'control terminals of said third switch means of said major and minor inverter circuits, major inverter circuit turn-off drive means and minor inverter circuit turn-off drive means for respectively rendering said first and second switch means of the'commondrive inverter circuit conductive over intervals corresponding to the desired conducting intervals of said third switch means to said major and minor inverter circuits. i i

6. An inverter circuit for cyclically driving two separate current control devices conductive in a conduction sequence wherein one of the current control devices is to be rendered conductive at a different time and more frequently than the other of same over a given cycle, each of said current control devices having load terminals and a control terminal which effects the conduction through the load terminals when voltage of the same given polarity is applied thereto, said inverter circuit comprising: a transformer having a center tapped primary winding and at least one center tapped secondary winding, a pair of D.C. input terminals connected between the center tap point on said primary winding and a common reference point, first and second switch means respectively connected between the ends of said primary winding and said reference point, means connecting the opposite ends of said center tapped secondpair of current control devices, and first and second control means for respectively controlling the conduction of said first and second switch means in accordance with the desired conduction patterns of said first and second current control devices, said first and second control means effecting cyclic conduction patterns of said first and second switch means wherein a summation of the conducting intervals of each of said first and second switch over a given cycle of operation is identical to provide balanced operation of the transformer.

7. The inverter circuit of claim 6 wherein said first and second current control devices and said first and second switch means are to be rendered conductive during spaced conducting intervals requiring cesession of current flow in said center tapped primary winding of the inverter circuit over prolonged intervals of time, and there is provided a second center tapped secondary winding on said transformer whose center tap point is connected to said common reference point and whose opposite ends thereof are coupled to a pair of rectifier means connected in the same sense to a common point, third switch means'connected between said common point and said common reference point, and control means for said third switch means for rendering the same conductiveduring those intervals when current flow is to cease said center tapped primary winding, conduction of said third switch means an'd one of said rectifier means establishing a low impedance shortcircuiting path across one of the halves ofsaid center tapped secondary winding.

8. An inverter circuit comprising: a transformer having a center tapped primary winding and at least one secondary winding, a pair of D.C. input terminals connected between the center tapped primary winding and a reference point, first and second means respectively connected between the ends of said primary winding and said reference point, control means for rendering said first and second switch means conductive respectively over spaced intervals of time wherein only one or the other of said switch means is conductive over any given interval and that interval is spaced from an interval during which the other switch means is to be rendered conductive, the conduction of said first and second switch means respectively resulting in current flow in opposite direction in different halves of .the center tapped primary winding, means for terminating current flow through said primary winding between the. spaced intervals during which the first and second switch means are conductive comprising a center tapped secondary winding of said transformer having a center tap point connected to said reference point and a pair of ary winding respectively to the control terminals of said rectifier means connected in the same sense to a common point, and third switch means connected between said common point and said reference point, and control means for rendering said third switch means conductive when termination in the current flow through both halves of said primary winding is desired, to establish a short circuit path through said third switch means and one of said rectifier means across one of the halves of said center tapped secondary winding.

9. A stepped alternating voltage generating circuit comprising: a transformer having a center-tapped primary winding and at least one secondary winding, a pair of D.C. input terminals connected between a center tap point on said primary winding and a reference point, first and second switch means respectively connected between the ends of said primary winding and said reference point, control means for alternately rendering said first and second switch means conductive to effect current flow sequentially in opposite directions through different halves of said primary winding, to generate pulses alternating in polarity in said secondary winding and spaced by intervals where the output is substantially zero, and turn-off means for ensuring the sudden and continued disappearance in the output across said secondary winding during said spaced intervals including third switch means connectable across at least the half of said primary winding carrying current at any instant, control means for rendering the latter switch means conductive during said spaced intervals, the conduction of said latter switch means resulting in a voltage drop thereacross which when applied across the primary winding will effect an imperfect zero output across said secondary winding, and zero output aiding means including means for applying a voltage in series with said switch means and said primary winding which substantially cancels the voltage otherwise applied across said primary winding halves during the period a zero output is desired.

10.;The circuit of claim!) wherein said third switch means is a current control device having a pair of load terminals connected in series with a center tap point of said primary winding and there is associated with said third switch means a pair'of rectifier means respectively coupled in the same sense to-the load terminal of said current control device remote from said primary winding; and said zero output aiding means comprises second transformer means having a primary winding and a pair of secondary windings respectively connected in an opposite sense between the opposite ends of said center tapped primary winding of the first mentioned transformer and said pair of rectifier means, and a source of alternating voltage connected to said primary winding of said second transformer means to produce in said respective secondary windings thereat voltages of a polarity which respectively cancel out the voltage drop across the associated rectifier means and said third switch means during the half cycle when the associated rectifier means is operative to shunt the associated primary winding half.

11. A stepped alternating voltage generating circuit comprising: a transformer having a center-tapped primary winding and at least one secondary winding, a pair of DC. input terminals connected between a center tap point on said primary winding and a reference point, first and second switch means respectively connected between the ends of said primary winding and said reference point, control means for alternately rendering said first and second switch means conductive to effect current flow sequentially in opposite directions through different halves of said primary winding to generate pulses alternating in polarity in said secondary winding and spaced by intervals where the output is substantially zero, and turn-off means for ensuring the sudden and continued disappearance in the output across said secondary winding during said spaced intervals including third switch means having' a pair of load terminals connected in series with the center tap point of said primary winding, and a pair of rectifier means respectively coupled in the same sense to the load terminal of said third switch means remote from said primary winding, and means comprising second transformer means having a primary winding and a pair of secondary windings respectively connected in an opposite sense between the opposite ends of said center tapped primary winding of the first mentioned transformer and'said pair of rectifier means, and a source of alternating voltage connected to said primary winding of said second transformer. 

1. A stepped alternating voltage generating circuit comprising: a transformer having a center tapped primary winding and at least one secondary winding: a source of D.C. voltage having a pair of D.C. output terminals, said D.C. output terminals being connected between a center tap point on said primary winding and a reference point; first and second switch means respectively connected between the ends of said primary winding and said reference point; control means for alternately rendering said switch means conductive during spaced intervals to effect current flow sequentially in opposite directions through different halves of said primary winding to generate pulses alternating in polarity in said secondary winding spaced by intervals where the output is substantially zero; and means for ensuring the sudden and continued disappearance in the output across said secondary winding during said spaced intervals including third switch means connectable across a winding of said transformer, and control means for rendering the latter switch means conductive during said spaced intervals wherein said third switch means is a current control device having a pair of load terminals connected in series with the center top point of said primary winding, and there is associated with said third switch means a pair of rectifier means connected respectively in the same sense between the load terminal of said current control device remote from said primary winding and the opposite ends of said primary winding, to form respective paths shunting the respective halves of the primary winding to bypass the current flow therethrough.
 2. A stepped alternating voltage generating circuit comprising: a major and a minor inverter circuit, each inverter circuit comprising a transformer having a primary winding and at least one secondary winding, a pair of D.C. voltage input terminals connected between a center tap point on said primary winding and a reference point, first and second switch means respectively connected between the ends of said primary windinG and said reference point, first control means for alternately rendering said first and second switch means conductive during spaced intervals to effect current flow sequentially in opposite directions through different halves of said primary winding to generate pulses alternating in polarity in said secondary winding spaced by intervals where the output is substantially zero, and means for ensuring the sudden and continued disappearance in the output across said secondary winding during said spaced intervals comprising third switch means connectable across a winding of said transformer and second control means for rendering the latter switch means conductive during said spaced intervals; the control means of said major and minor bridge circuits rendering the associated first, second and third switch means conductive in different but complementary conduction patterns so the summation of the outputs of the secondary windings of the associated transformers produces a stepped, sinusoidal-like waveform; and means connecting the secondary windings of the transformers of said major and minor bridge circuits in series voltage additive relation.
 3. The circuit of claim 2 wherein said third switch means of each inverter circuit is a current control device having a pair of load terminals connected in series with the center tap point of said primary winding and a control terminal which effects conduction of the switch means when a drive signal of a given polarity is fed thereto by said second control means, and there is associated with each third switch means a pair of rectifier devices respectively coupled in the same sense between the load terminal of said current control device remote from said primary winding and the opposite ends of said primary winding, to form respective paths shunting the respective halves of the primary winding to bypass the current flowing therethrough.
 4. The circuit of claim 2 where the conduction pattern of the first, second and third switch means of said major inverter circuit is that said first and second switch means are identically alternately rendered conductive during successive half cycles, each such switch means having one conducting interval occupying a majority of and centered in the half cycle involved, leaving relatively narrow non-conducting intervals at the beginning and end of the half cycle, and the third switch means is conductive during the intervals when said first and second switch means are not conductive; the conduction pattern of the first, second and third switch means of said minor inverter circuit is that said first and second switch means are identically alternately rendered conductive during successive half cycles, each such switch means having during each half cycle when the same is conductive a half cycle centered conducting interval and conducting intervals corresponding to said narrow non-conducting intervals of the corresponding switch means of the major inverter circuit.
 5. The circuit of claim 3 wherein the conduction pattern of the first, second and third switch means of said major inverter circuit is that said first and second switch means are identically alternately rendered conductive during successive half cycles, each such switch means having only one conducting interval occupying a majority of and centered in the half cycle involved, leaving relatively narrow non-conducting intervals at the beginning and end of the half cycle, and the third switch means is conductive during the intervals when said first and second switch means are not conductive; the conduction pattern of the first, second and third switch means of said minor inverter circuit is that said first and second switch means are identically alternately rendered conductive during successive half cycles, each such switch means having during each half cycle when the same is conductive only a half cycle centered conducting interval and conducting intervals corresponding to said narrow non-conducting intervals of the corresponding switch means of the major Inverter circuit; the sum of the non-conducting intervals of the first and second switch means of the major inverter circuit over each cycle thereof being substantially the same as the sum of the non-conducting intervals of the first and second switch means of the minor inverter circuit; and said second control means of the said major and minor inverter circuits being a common inverter drive circuit comprising a transformer having a center-tapped primary winding and at least one secondary winding, a source of D.C. voltage having a pair of D.C. output terminals, said D.C. output terminals being connected between a center tap point on said primary winding and a reference point, first and second switch means respectively connected between the ends of said primary winding and said reference point, the latter secondary winding having a center tap point coupled to said reference point of said major and minor inverter circuits and the opposite ends thereof being respectively connected to said control terminals of said third switch means of said major and minor inverter circuits, major inverter circuit turn-off drive means and minor inverter circuit turn-off drive means for respectively rendering said first and second switch means of the common drive inverter circuit conductive over intervals corresponding to the desired conducting intervals of said third switch means of said major and minor inverter circuits.
 6. An inverter circuit for cyclically driving two separate current control devices conductive in a conduction sequence wherein one of the current control devices is to be rendered conductive at a different time and more frequently than the other of same over a given cycle, each of said current control devices having load terminals and a control terminal which effects the conduction through the load terminals when voltage of the same given polarity is applied thereto, said inverter circuit comprising: a transformer having a center tapped primary winding and at least one center tapped secondary winding, a pair of D.C. input terminals connected between the center tap point on said primary winding and a common reference point, first and second switch means respectively connected between the ends of said primary winding and said reference point, means connecting the opposite ends of said center tapped secondary winding respectively to the control terminals of said pair of current control devices, and first and second control means for respectively controlling the conduction of said first and second switch means in accordance with the desired conduction patterns of said first and second current control devices, said first and second control means effecting cyclic conduction patterns of said first and second switch means wherein a summation of the conducting intervals of each of said first and second switch over a given cycle of operation is identical to provide balanced operation of the transformer.
 7. The inverter circuit of claim 6 wherein said first and second current control devices and said first and second switch means are to be rendered conductive during spaced conducting intervals requiring cesession of current flow in said center tapped primary winding of the inverter circuit over prolonged intervals of time, and there is provided a second center tapped secondary winding on said transformer whose center tap point is connected to said common reference point and whose opposite ends thereof are coupled to a pair of rectifier means connected in the same sense to a common point, third switch means connected between said common point and said common reference point, and control means for said third switch means for rendering the same conductive during those intervals when current flow is to cease in said center tapped primary winding, conduction of said third switch means and one of said rectifier means establishing a low impedance short-circuiting path across one of the halves of said center tapped secondary winding.
 8. An inverter circuit comprising: a tRansformer having a center tapped primary winding and at least one secondary winding, a pair of D.C. input terminals connected between the center tapped primary winding and a reference point, first and second means respectively connected between the ends of said primary winding and said reference point, control means for rendering said first and second switch means conductive respectively over spaced intervals of time wherein only one or the other of said switch means is conductive over any given interval and that interval is spaced from an interval during which the other switch means is to be rendered conductive, the conduction of said first and second switch means respectively resulting in current flow in opposite direction in different halves of the center tapped primary winding, means for terminating current flow through said primary winding between the spaced intervals during which the first and second switch means are conductive comprising a center tapped secondary winding of said transformer having a center tap point connected to said reference point and a pair of rectifier means connected in the same sense to a common point, and third switch means connected between said common point and said reference point, and control means for rendering said third switch means conductive when termination in the current flow through both halves of said primary winding is desired, to establish a short circuit path through said third switch means and one of said rectifier means across one of the halves of said center tapped secondary winding.
 9. A stepped alternating voltage generating circuit comprising: a transformer having a center-tapped primary winding and at least one secondary winding, a pair of D.C. input terminals connected between a center tap point on said primary winding and a reference point, first and second switch means respectively connected between the ends of said primary winding and said reference point, control means for alternately rendering said first and second switch means conductive to effect current flow sequentially in opposite directions through different halves of said primary winding, to generate pulses alternating in polarity in said secondary winding and spaced by intervals where the output is substantially zero, and turn-off means for ensuring the sudden and continued disappearance in the output across said secondary winding during said spaced intervals including third switch means connectable across at least the half of said primary winding carrying current at any instant, control means for rendering the latter switch means conductive during said spaced intervals, the conduction of said latter switch means resulting in a voltage drop thereacross which when applied across the primary winding will effect an imperfect zero output across said secondary winding, and zero output aiding means including means for applying a voltage in series with said switch means and said primary winding which substantially cancels the voltage otherwise applied across said primary winding halves during the period a zero output is desired.
 10. The circuit of claim 9 wherein said third switch means is a current control device having a pair of load terminals connected in series with a center tap point of said primary winding and there is associated with said third switch means a pair of rectifier means respectively coupled in the same sense to the load terminal of said current control device remote from said primary winding; and said zero output aiding means comprises second transformer means having a primary winding and a pair of secondary windings respectively connected in an opposite sense between the opposite ends of said center tapped primary winding of the first mentioned transformer and said pair of rectifier means, and a source of alternating voltage connected to said primary winding of said second transformer means to produce in said respective secondary windings thereat voltages of a polarity which respectively cancel out the voltage drop across the associated recTifier means and said third switch means during the half cycle when the associated rectifier means is operative to shunt the associated primary winding half.
 11. A stepped alternating voltage generating circuit comprising: a transformer having a center-tapped primary winding and at least one secondary winding, a pair of D.C. input terminals connected between a center tap point on said primary winding and a reference point, first and second switch means respectively connected between the ends of said primary winding and said reference point, control means for alternately rendering said first and second switch means conductive to effect current flow sequentially in opposite directions through different halves of said primary winding to generate pulses alternating in polarity in said secondary winding and spaced by intervals where the output is substantially zero, and turn-off means for ensuring the sudden and continued disappearance in the output across said secondary winding during said spaced intervals including third switch means having a pair of load terminals connected in series with the center tap point of said primary winding, and a pair of rectifier means respectively coupled in the same sense to the load terminal of said third switch means remote from said primary winding, and means comprising second transformer means having a primary winding and a pair of secondary windings respectively connected in an opposite sense between the opposite ends of said center tapped primary winding of the first mentioned transformer and said pair of rectifier means, and a source of alternating voltage connected to said primary winding of said second transformer. 